Maxim MAX5865 Uživatelský manuál stáhnout pdf

General Description

The MAX5865 ultra-low-power, highly integrated analog

front end is ideal for portable communication equipment

such as handsets, PDAs, WLAN, and 3G wireless termi-

nals. The MAX5865 integrates dual 8-bit receive ADCs

and dual 10-bit transmit DACs while providing the high-

est dynamic performance at ultra-low power. The ADCs’

analog I-Q input amplifiers are fully differential and

accept 1V

P-P

full-scale signals. Typical I-Q channel

phase matching is ±0.2° and amplitude matching is

±0.05dB. The ADCs feature 48.4dB SINAD and 70dBc

spurious-free dynamic range (SFDR) at f

= 5.5MHz and

CLK

= 40MHz. The DACs’ analog I-Q outputs are fully

differential with ±400mV full-scale output, and 1.4V com-

mon-mode level. Typical I-Q channel phase matching is

±0.15° and gain matching is ±0.05dB. The DACs also

feature dual 10-bit resolution with 72dBc SFDR, and

57dB SNR at f

OUT

= 2.2MHz and f

CLK

= 40MHz.

The ADCs and DACs operate simultaneously or indepen-

dently for frequency-division duplex (FDD) and time-divi-

sion duplex (TDD) modes. A 3-wire serial interface

controls power-down and transceiver modes of opera-

tion. The typical operating power is 75.6mW at f

CLK

40Msps with the ADCs and DACs operating simultane-

ously in transceiver mode. The MAX5865 features an

internal 1.024V voltage reference that is stable over the

entire operating power-supply range and temperature

range. The MAX5865 operates on a +2.7V to +3.3V ana-

log power supply and a +1.8V to +3.3V digital I/O power

supply for logic compatibility. The quiescent current is

8.5mA in idle mode and 1µA in shutdown mode. The

MAX5865 is specified for the extended (-40°C to +85°C)

temperature range and is available in a 48-pin thin QFN

package.

Applications

Narrowband/Wideband CDMA Handsets

and PDAs

Fixed/Mobile Broadband Wireless Modems

3G Wireless Terminals

Features

♦ Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs

♦ Ultra-Low Power

75.6mW at f

CLK

= 40MHz (Transceiver Mode)

64mW at f

CLK

= 22MHz (Transceiver Mode)

Low-Current Idle and Shutdown Modes

♦ Excellent Dynamic Performance

48.4dB SINAD at f

= 5.5MHz (ADC)

70dB SFDR at f

OUT

= 2.2MHz (DAC)

♦ Excellent Gain/Phase Match

±0.2° Phase, ±0.05dB Gain at f

= 5.5MHz (ADC)

♦ Internal/External Reference Option

♦ +1.8V to +3.3V Digital Output Level (TTL/CMOS

Compatible)

♦ Multiplexed Parallel Digital Input/Output for

ADCs/DACs

♦ Miniature 48-Pin Thin QFN Package (7mm

7mm)

♦ Evaluation Kit Available (Order MAX5865EVKIT)

MAX5865

Ultra-Low-Power, High-Dynamic-

Performance, 40Msps Analog Front End

________________________________________________________________ Maxim Integrated Products 1

ADC

IA+

IA-

QA+

QA-

ID+

ID-

QD+

QD-

REFP

COM

REFN

DIN

SCLK

REFIN

DAC

ADC

OUTPUT

MUX

DAC

INPUT

MUX

CLK

DA0–DA7

DD0–DD9

MAX5865

REF AND

BIAS

SERIAL

INTERFACE

AND SYSTEM

CONTROL

Functional Diagram

19-2916; Rev 1; 10/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX5865ETM -40°C to +85°C

48 Thin QFN-EP*

(7mm x 7mm)

MAX5865E/D -40°C to +85°C Dice**

*EP = Exposed paddle.

**Contact factory for dice specifications.

Pin Configuration appears at end of data sheet.

1 2 3 4 5 6 ... 25 26

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Strany 1 - Ordering Information

General DescriptionThe MAX5865 ultra-low-power, highly integrated analogfront end is ideal for portable communication equipmentsuch as handsets, PDAs,

Strany 2 - ELECTRICAL CHARACTERISTICS

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End10 _________________________________________________________________________

Strany 3 - Residual DC offset error

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End____________________________________________________________________________

Strany 4 - -130.9 dBc/Hz

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End12 _________________________________________________________________________

Strany 5

Detailed DescriptionThe MAX5865 integrates dual 8-bit receive ADCs anddual 10-bit transmit DACs while providing ultra-lowpower and highest dynamic per

Strany 6

MAX5865Dual 8-Bit ADCThe ADC uses a seven-stage, fully differential,pipelined architecture that allows for high-speed con-version while minimizing pow

Strany 7 - ADC CHANNEL-QA FFT PLOT

ADC System Timing RequirementsFigure 3 shows the relationship between the clock, ana-log inputs, and the resulting output data. Channel IA(CHI) and ch

Strany 8 - MAX5865 toc04

MAX5865DAC TimingFigure 4 shows the relationship between the clock, inputdata, and analog outputs. Data for the I channel (ID) islatched on the fallin

Strany 9

Shutdown mode offers the most dramatic power sav-ings by shutting down all the analog sections of theMAX5865 and placing the ADCs’ digital outputs in

Strany 10

MAX5865Mode Recovery TimingFigure 6 shows the mode recovery timing diagram.tWAKEis the wake-up time when exiting shutdown, idle,or standby mode and en

Strany 11

Clock jitter is especially critical for undersamplingapplications. Consider the clock input as an analoginput and route away from any analog input or

Strany 12 - Pin Description

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End2 __________________________________________________________________________

Strany 13 - Detailed Description

MAX5865Using Op-Amp CouplingDrive the MAX5865 ADCs with op amps when a baluntransformer is not available. Figures 9 and 10 show theADCs being driven b

Strany 14 - Table 1, Figure 2). The

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End____________________________________________________________________________

Strany 15 - Dual 10-Bit DAC

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End22 _________________________________________________________________________

Strany 16 - Operation Modes

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front EndDAC Offset ErrorOffset error (Figure 12a) is the difference between theideal

Strany 17

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End24 _________________________________________________________________________

Strany 18 - System Clock Input (CLK)

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End____________________________________________________________________________

Strany 19 - Applications Information

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front EndMaxim cannot assume responsibility for use of any circuitry other than circu

Strany 20 - FDD and TDD Modes

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End____________________________________________________________________________

Strany 21 - PROCESSOR

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End4 __________________________________________________________________________

Strany 22 - Dynamic Parameter Definitions

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End____________________________________________________________________________

Strany 23

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End6 __________________________________________________________________________

Strany 24 - Pin Configuration

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End____________________________________________________________________________

Strany 25 - Package Information

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End8 __________________________________________________________________________

Strany 26 - DOCUMENT CONTROL NO.APPROVAL

MAX5865Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End____________________________________________________________________________

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Maxim MAX5865 Uživatelský manuál

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